1. Field of the Invention
This invention relates generally to a random access memory (RAM) circuits. More particularly, this invention relates to static RAM circuits. Even more particularly, this invention relates to integrated nonvolatile static RAM (NVSRAM) circuits.
2. Description of Related Art
Static random access memory (SRAM) is well known in the art and consists of a bistable transistor flip-flop or latching circuit. Referring to FIGS. 1a and 1b, the inverters I1 5 and I2 10 are coupled such that the output of the inverter I1 5 is connected to the input of the inverter I2 10 and the output of the inverters I2 10 is connected to the input of the inverter I1 5 to form the bistable latch. The access transistor Ma1 15 has a first source/drain terminal connected to the input of the inverter I1 5 and the output of the inverter I2 10 and a second source/drain terminal connected to the bit line BL 25. The access transistor Ma2 20 has a first source/drain terminal connected to the input of the inverter I2 10 and the output of the inverter I1 5 and a second source/drain terminal connected to the bit line BL 30. The gates of the access transistors Ma1 15 and Ma2 20 are connected to the word line WL 35 to receive the activation signals for accessing the memory cell.
In operation, the bit lines BL 25 and BL 30 are precharged respectively to the data to be written or read from the memory cell. The word Line WL 35 is set to a voltage level sufficient to activate the access transistors Ma1 15 and Ma2 20 and the digital signal representative of the binary data to be written to or read from the memory cell is transferred to or from the memory cell.
The inverter I1 5 consists of the n-type MOS transistor Mn1 9 and the p-type MOS transistor Mp1 7 configured as the well known CMOS inverter. Similarly the inverter I2 10 consists of the n-type MOS transistor Mn2 13 and the p-type MOS transistor Mp2 11 also configured a CMOS inverter. The gates of the n-type MOS transistor Mn1 9 and the p-type MOS transistor Mp1 7 are connected to the common drain connection of the n-type MOS transistor Mn2 13 and the p-type MOS transistor Mp2 11 and the gates of the n-type MOS transistor Mn2 13 and the p-type MOS transistor Mp2 11 are connected to the common drain connection of the n-type MOS transistor Mn1 9 and the p-type MOS transistor Mp1 7. This forms the cross-connection to create the bistable flip-flop. The sources of the gates of the n-type MOS transistor Mn1 9 and the p-type MOS transistor Mp1 7 are connected to the common drain connection of the n-type MOS transistors Mn2 13 and Mn1 9 are connected to the ground reference voltage source and the sources of the p-type MOS transistors Mp1 7 and Mp2 11 are connected to the power supply voltage source VDD.
As stated above, the bit lines BL 25 and BL 30 are precharged for performing desired writing and read from the SRAM cell. For instance if the digital signals representing a binary 1 are to be written to the SRAM cell, the bit line BL 25 is set to the voltage of the power supply voltage source VDD less a voltage threshold VT of an MOS transistor and the bit line BL 30 is set to essentially the ground voltage level. The word Line WL 35 is set to a voltage level sufficient to activate the access transistors Ma1 15 and Ma2 20. The digital signal representing the binary 1 turns on the n-type MOS transistor Mn2 13 and turns off the p-type MOS transistor Mp2 11. The complementary binary 0 present at the bit line BL 30 turns on the p-type MOS transistor Mp1 7 and turns off the n-type MOS transistor Mn1 9, thus setting the flip-flop For reading the SRAM cell, the bit lines BL 25 and BL 30 are precharged to a level approximately equal to one half of the voltage level of the power supply voltage source VDD and the word Line WL 35 is set to the voltage level sufficient to activate the access transistors Ma1 15 and Ma2 20. The digital signals present at the drains of the n-type MOS transistor Mn1 9 and the p-type MOS transistor Mp1 7 are transferred to the bit line BL 25 and the digital signals present at the n-type MOS transistor Mn2 13 and the p-type MOS transistor Mp2 11 is transferred to the bit line BL 30. The bit lines BL 25 and BL 30 are connected to a bit line sense amplifier to regenerate the binary data.
The data retained in the memory cell is volatile, in that any interruption of the power supply voltage source causes a loss of the data. An alternative to the volatile SRAM is the nonvolatile RAM. The nonvolatile RAM consists of a floating gate transistor which has a charge placed on a floating gate to modify the voltage threshold VT of the floating gate transistor that indicates the state of the binary data retained in the nonvolatile RAM cell. The cell structure and application of the nonvolatile RAM is well known in the art. The nonvolatile RAM has three classifications the Electrically Programmable Read Only Memory (EPROM), Erasable and Programmable Read Only Memory (EEPROM), and the flash Electrically Erasable and Programmable Read Only Memory (Flash). The EPROM is programmed by electrically forcing charge to the floating gate. Ultra-violet light is employed to eliminate (erase) the electrical charges of the programming from the floating gate of the EPROM. During EPROM program operation, in addition to a low-voltage power supply (VDD), an external high-voltage programming power supply (VPP) of about 12V is used. With a sealed package, UV-light cannot reach floating-gate, thus the erase operation is blocked and the EPROM is considered a One Time Programmable (OTP) EPROM. If the sealed OTP is changed to sealed Flash, then both erase and program operations can be performed electrically and repeatedly in system without the overheads of UV-light exposure and the external VPP programmer due to Flash's on-chip charge pump that can generate high voltage internally.
The nonvolatile RAM or Flash memory offers a medium read speed of around 50 ns but a very slow write speed of a few milliseconds (ms). The reason for such a slow write speed in today's flash memory cells are mainly due to its slow program and erase schemes based on device FN tunneling. The FN-tunneling effect allows the electrons to be injected into or removed from flash's floating gate that is used to store the data. In order to have a successful FN tunneling effect, the electric field across the tunneling oxide has to be maintained larger than 10V/cm. That is the reason why most of the flash memory requires a charge pump to generate on-chip high-voltage for erase and program operations.
There is a need to have a random access memory that offers the same fast read and write speed as conventional SRAM in 10 nS range and while retaining the non-volatility of flash to retain its data when power loss occurs.
U.S. Pat. No. 5,488,579 (Sharma, et al.) details a nonvolatile SRAM cell that includes a six-transistor SRAM cell and a three-transistor nonvolatile memory portion. The nonvolatile memory portion is connected to one storage node of the SRAM cell portion.
U.S. Pat. No. 5,464,998 (Hayakawa, et al.) provides a non-volatile semiconductor memory device that includes NAND type memory cells arranged in a matrix pattern over a semiconductor substrate and channel stopper layers. The channel stopper layers separate adjacent NAND type memory cells.
U.S. Pat. No. 6,038,170 (Shiba) describes a nonvolatile memory with a hierarchical bit line structure. Sub-bit lines within the hierarchical structure are connected to an appropriate main bit line through a first and a second selection MOS transistor. The first selection MOS transistor has a thin gate insulating film and is used for read operations only. The second MOS transistor has a thick gate insulating film and is used at least for write operations.